The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation.
Shin-Etsu Support Jig Handles Thin Wafers for Reflow Soldering Kenji Tsuda, Asia Contributing Editor - 01/05/2009
Shin-Etsu Polymer Co. Ltd. has developed a jig for handling thin wafers that can endure 260°C in a solder reflow furnace. The tool makes it possible to use a silicone film to attach solder balls to thinned wafers for 3-D stacked chips. More
ASAT Prepares for Lower Sales in Fiscal 2Q09 Staff - 12/17/2008
ASAT Holdings Ltd. today announced that revenue was up in the first quarter of fiscal 2009, but preliminary results show that numbers will be down again in the second fiscal quarter.
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Dalsa Semiconductor to License Alchimer’s TSV Coating Technology Staff - 12/17/2008
Wafer foundry Dalsa Semiconductor has successfully created conformal copper seed layers on through-silicon via (TSV) structures using the eG ViaCoat process from Alchimer SA. As a result of the successful tests, Dalsa intends to license Alchimer’s technology to enhance its MEMS production capabilities.
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STATS ChipPAC to Lay Off 1600 in Latest Restructuring Staff - 12/17/2008
STATS ChipPAC Ltd. (Singapore) has responded to the global semiconductor downturn with a restructuring plan that results in ~12% of the company’s workforce being laid off.
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IEDM Panel: Processing Costs Headed Up David Lammers, News Editor - 12/17/2008
With more expensive tools and new process modules coming, IC manufacturers will struggle to maintain the cost-per-function reductions that have broadened the market for semiconductors. The likely introduction of 3-D interconnects, vertical transistors and EUV lithography all will add pressure on wafer processing costs, experts said at an evening panel discussion at the International Electron Devices Meeting going on in San Francisco this week.
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Japan’s 3-D R&D Consortium Takes Shape Kenji Tsuda, Asia Contributing Editor - 12/08/2008
At SEMICON Japan, managers of the government-backed 3-D IC technology development project outlined the project’s goals. Also at the show, managers from Accretech, Applied Materials and EV Group described their TSV-specific agendas, including new tools for 3-D interconnect applications.
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IEDM Showcases Medical Device Research David Lammers, News Editor - 12/04/2008
Researchers from IMEC and several U.S. universities will go to the upcoming IEDM conference with presentations on implantable medical devices and drug delivery systems. The work includes innovative wafer-level packaging techniques and neural implants with dense electrode arrays. Researchers also are developing implantable drug packages that can be released on command to attack tumors or revive a wounded soldier.
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Rudolph NSX Selected for Inspection of TSV Process Staff - 12/03/2008
Rudolph Technologies Inc. said that it has installed an NSX 115 Macro Inspection System at a major European fab. The NSX tool performs 2-D and 3-D metrology and inspection of defects during the same production cycle.
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Technical Articles
Flow-Over-Wire Materials Enable Die Stacking Michael Todd, Henkel Corp., Irvine, Calif., 12/01/2008
Recent advances in flow-over-wire (FOW) technologies, including FOW pastes and films, are enabling packaging engineers to design thinner packages, reduce manufacturing process steps and drive down overall package costs....
3-D ICs Enter Commercialization Philip Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, N.C., 11/01/2008
Among many manufacturers — Micron, Toshiba, STMicroelectronics, Intel, Chartered Semiconductor and TSMC — 3-D integration using through-silicon vias is imminent....
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Flow-Over-Wire Materials Enable Die Stacking
